Book by March 17 for lowest rates on the SEMI U Pre-show Training. The cost of the courses go up on March 18 by $100.
Kick-off your conference experience with SEMI U! For the first time in the Midwest, SEMI U will be offering a variety in-person, instructor-led trainings at SEMIEXPO Heartland. These trainings will be hosted the day before the event on Monday, March 31.
Indiana Convention Center
Rooms: TBD
9:30am - 5:00pm
Pass Fees + $795*
$895*
+ $795* in addition to fees already paid.
* The cost will be $100 more after March 17
Trainings Available
SEMI U: Understanding Semiconductor Technology and Business Training
SEMI U: Understanding Semiconductor Technology and Business Training
The first part of the course provides a brief overview of semiconductor design and fabrication steps, encompassing IC design techniques, all wafer processing steps, assembly, and packaging. It delves into semiconductor jargon in laypeople terms, and various substrate types such as Si, SiGe, FDSOI, GaAs, SiC, GaN. Additionally, it discusses different types of transistors like pMOS, nMOS, Bipolar, BiCMOS, CMOS, FinFets, and GAA and their evolution and what applications they are used in.
The second part of the course focuses on semiconductor business aspects such as silicon economics, wafer processing costs, semiconductor revenue forecasts, driving forces in the industry, top semiconductor IDMs, market competitors based on market share, OEMs, foundries, top tool vendors, and Fabless companies. Addresses the fastest-growing semiconductor markets based on geographic locations and applications, identifies semiconductor competitors/customers, and discusses major semiconductor markets like Automotive, PC, Mobile, Memory, Wireless, Cell phones, Consumer, Gaming, AI, IoT, Digital TV, Radio, Automotive, MEMS, and Emerging Technology & Impact on Industry.
This course is suitable for anyone seeking a better understanding of the semiconductor industry, market leaders, terminology, business, and the semiconductor ecosystem.
Learning Objectives:
- Understand the fundamental principles and theories semiconductor technology.
- Communicate with other associates and understand wafer processing steps.
- Understand semiconductor business aspects such as silicon economics, wafer processing costs, semiconductor revenue forecasts, driving forces in the industry, top semiconductor IDMs, market competitors based on market share, OEMs, foundries, top tool vendors, and Fabless companies.
- Review the semiconductor eco-system as it relates to design and fabrication of a semiconductor device.
- Gain knowledge of major semiconductor markets like Automotive, PC, Mobile, Memory, Wireless, Cell phones, Consumer, Gaming, AI, IoT, Automotive, MEMS, and Emerging Technology & Impact on Industry.
- Demonstrate effective communication skills through written reports, presentations, and discussions related to semiconductor subjects.
- Collaborate effectively with peers in group projects or discussions regarding semiconductor subjects.
- Analyze and evaluate research literature in semiconductor technology.
- Develop critical thinking and problem-solving skills applicable to semiconductor technology.
Training by: Denny Frye, Instructor, PT International
Denny Frye is the CEO of PT International, LLC and has taught over 3000 seminars on semiconductor technology since 1978. He has been invited to teach on-site to industry giants such as Intel, Apple, Applied Materials, KLA, Bell Labs, ST Micro, NXP, Lam Research, IBM, Analog Devices, Qualcomm, Nvidia and hundreds more. His ability to teach complex subject matter to technical and non-technical students has made him a favorite presenter. He also worked for Western Electric as a semiconductor and systems engineer, NSA and the Underground Pentagon.
SEMI U: Smart Manufacturing & AI
SEMI U: Smart Manufacturing & AI
Immerse yourself in a full-day learning experience and gain an overview of cutting-edge technologies impacting the semiconductor industry. This course is intended for engineers, technicians, managers, and leaders.
Learning Objectives:
- Summarize key concepts of smart manufacturing and AI.
- Explain the roles of digital twins, automation, and data analytics.
- Understand opportunities to implement AI & smart manufacturing practices.
- Identify the benefits of integrating AI in semiconductor manufacturing.
Training by: Sirisha Kuchimanchi
Dr. Sirisha Kuchimanchi is a seasoned semiconductor executive and the founder of Sahita Technologies, a company dedicated to providing advanced manufacturing, semiconductor, and workforce development solutions. With over 20 years of experience in engineering, manufacturing, quality, and technology development, she has made significant contributions to the industry. At Texas Instruments, Sirisha led quality initiatives for a major manufacturing facility, driving improvements in key performance indicators with internal and external customers while fostering a high-performance team. Sirisha’s career began at Applied Materials, where she specialized in PVD Endura systems.
Sirisha is deeply committed to workforce development in the semiconductor sector, collaborating with industry, academia and government while also serving on the SRC Workforce Advisory Board. She holds a Ph.D. in Materials Science and Engineering from Carnegie Mellon University and has authored over 14 peer-reviewed publications and one patent.
Beyond her technical expertise, Sirisha is a champion for diversity and inclusion, having co-chaired the Technology & Manufacturing Women’s ERG at Texas Instruments, supporting over 500 employees globally. She also hosted the top 30% Spotify podcast “Women, Career & Life” and is a recognized TEDx speaker, conference panelist and speaker where she shares her insights on manufacturing, AI, and leadership with a global audience.
SEMI U: Advanced IC Packaging & Assembly: Techniques & Trends
SEMI U: Advanced IC Packaging & Assembly: Techniques & Trends
This course addresses IC packaging, assembly, and chip/substrate interconnections. It stresses the impact of the IC and end product requirements, i.e., “smaller, better, cheaper” and their influence on the manufacturing processes. Topics include all types of packages including ball grid arrays, flip chip, fanout, leadframe, stacked die, stacked packages, System-in-Package, and chip scale packages, and assembly technologies – Chip & Wire, Tape Automated Bonding, and Flip Chip. The growing importance of packaging as a way to deliver high integration and performance in today's products through heterogeneous integration of chiplets or 3D hybrid bonding will be discussed. This course is suitable for anyone seeking a better understanding of the assembly and packaging of semiconductor devices.
Learning Objectives:
- Recognize advanced packaging trends of emerging technologies and market demand and drivers
- Identify types of semiconductor packaging including different packaging techniques and selection criteria
- Classify material properties and applications and thermal and mechanical properties for packaging
- Explain assembly techniques and equipment including key assembly processes and equipment and tooling requirements
- Discover reliability and testing protocols including stress testing and failure analysis
- Describe thermal challenges and cooling solutions for thermal management in packaging
- Discuss eco-friendly packaging solutions and regulatory compliance regarding envrionnmental and sustainability considerations
- Predict future directions and innovations of advanced packaging including quantum and neuromorphic packaging and the roadmap for the next decade
Training By: Paul Hoffman, President, Sapient Focus
Paul Hoffman started his career at IBM working on flip chip and other packages. His decades of direct experience includes most types of packages such as wirebond, flip chip, ceramic, laminate, TAB, CSP, MCM, memory cards and others. While at Amkor as the head of Advanced Package Development he had the opportunity to understand the needs of customers worldwide across all applications and to direct the development of packages to meet those needs. One of those developments was very high production volume packages combining chips and SMT passives – and to describe those packages he coined the term “System in Package” or SiP in wide use today to extend the scope of packaging and contribute to the “More than Moore” era of electronics. He also spends time working with clients to understand patent and IP issues related to packaging and semiconductor processing. Paul has published many papers related to IC packaging and has over 40 issued patents, mostly in IC packaging.
MS Engineering Management/ Stanford Univ
BS Mechanical Eng/ Stanford Univ
Pass Fees + $795*
$895*
+ $695* in addition to fees already paid.
* The cost will be $100 more after March 17